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Advanced Information
CAT25C01/02/04/08/16
1K/2K/4K/8K/16K SPI Serial CMOS E
2
PROM
FEATURES
10 MHz SPI Compatible
1,000,000 Program/Erase Cycles
1.8 to 6.0 Volt Operation
100 Year Data Retention
Hardware and Software Protection
Self-Timed Write Cycle
8-Pin DIP/SOIC, 8/14-Pin TSSOP and 8-Pin MSOP
Zero Standby Current
16/32-Byte Page Write Buffer
Low Power CMOS Technology
SPI Modes (0,0 & 1,1)
Block Write Protection
– Protect 1/4, 1/2 or all of E
2
PROM Array
Commercial, Industrial and Automotive
Temperature Ranges
DESCRIPTION
The CAT25C01/02/04/08/16 is a 1K/2K/4K/8K/16K Bit
SPI Serial CMOS E
2
PROM internally organized as
128x8/256x8/512x8/1024x8/2048x8 bits. Catalyst’s ad-
vanced CMOS Technology substantially reduces de-
vice power requirements. The CAT25C01/02/04 fea-
tures a 16-byte page write buffer. The 25C08/16 fea-
tures a 32-byte page write buffer.The device operates
via the SPI bus serial interface and is enabled though a
Chip Select (CS). In addition to the Chip Select, the clock
input (SCK), data in (SI) and data out (SO) are required
to access the device. The HOLD pin may be used to
suspend any serial communication without resetting the
serial sequence. The CAT25C01/02/04/08/16 is de-
signed with software and hardware write protection
features including Block Write protection. The device is
available in 8-pin DIP, 8-pin SOIC, 8-pin MSOP and 8/
14-pin TSSOP packages.
PIN CONFIGURATION
TSSOP Package (U14)
SOIC Package (S)
DIP Package (P)
TSSOP Package (U)
CS
1
2
3
4
5
6
7
14
VCC
CS
1
2
3
4
8
7
6
5
V
CC
CS
1
2
3
4
8
7
6
5
V
CC
HOLD
SCK
SI
CS
1
2
3
4
8
7
6
5
V
CC
SO
WP
HOLD
SO
WP
SO
HOLD
SO
13
HOLD
SCK
SI
WP
SCL
NC
12
NC
NC
V
SS
SI
V
SS
NC
11
V
SS
10
NC
NC
BLOCK DIAGRAM
WP
9
SCK
SI
MSOP Package (R)*
V
SS
8
SENSE AMPS
SHIFT REGISTERS
CS
1
2
3
4
8
7
6
5
V
CC
SO
WP
HOLD
SCK
SI
V
SS
COLUMN
DECODERS
WORD ADDRESS
BUFFERS
*CAT 25C01/02 only
PIN FUNCTIONS
Pin Name
Function
SO
I/O
CONTROL
SI
CS
WP
HOLD
SCK
SO
Serial Data Output
E
2
PROM
ARRAY
SCK
Serial Clock
SPI
CONTROL
LOGIC
XDEC
WP
Write Protect
V
CC
+1.8V to +6.0V Power Supply
BLOCK
PROTECT
LOGIC
V
SS
Ground
CS
Chip Select
DATA I N
STORAGE
SI
Serial Data Input
HOLD
Suspends Serial Input
HIGH VOLTAGE/
TIMING CONTROL
NC
No Connect
STATUS
REGISTER
25C128 F02
© 1999 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
1
Doc. No. 25067-00 5/00
CAT25C01/02/04/08/16
Advanced Information
ABSOLUTE MAXIMUM RATINGS*
*COMMENT
Temperature Under Bias ................. –55
C to +125
C
Stresses above those listed under “Absolute Maximum
Ratings” may cause permanent damage to the device.
These are stress ratings only, and functional operation
of the device at these or any other conditions outside of
those listed in the operational sections of this specifica-
tion is not implied. Exposure to any absolute maximum
rating for extended periods may affect device perfor-
mance and reliability.
Storage Temperature ....................... –65
C to +150
C
Voltage on any Pin with
Respect to V
SS
(1)
.................. –2.0V to +V
CC
+2.0V
V
CC
with Respect to V
SS
................................
–2.0V to +7.0V
Package Power Dissipation
Capability (Ta = 25
C
Output Short Circuit Current
(2)
........................ 100 mA
RELIABILITY CHARACTERISTICS
Symbol
Parameter
Min.
Max.
Units
Reference Test Method
N
END
(3)
Endurance
1,000,000
Cycles/Byte
MIL-STD-883, Test Method 1033
T
DR
(3)
Data Retention
100
Years
MIL-STD-883, Test Method 1008
V
ZAP
(3)
ESD Susceptibility
2000
Volts
MIL-STD-883, Test Method 3015
I
LTH
(3)(4)
Latch-Up
100
mA
JEDEC Standard 17
D.C. OPERATING CHARACTERISTICS
V
CC
= +1.8V to +6.0V, unless otherwise specified.
Limits
Symbol
Parameter
Min.
Typ.
Max.
Units
Test Conditions
I
CC1
Power Supply Current
5
mA
V
CC
= 5V @ 5MHz
(Operating Write)
SO=open; CS=Vss
I
CC2
Power Supply Current
3
mA
V
CC
= 5.5V
(Operating Read)
F
CLK
= 5MHz
I
SB
Power Supply Current
0
A CS = V
CC
(Standby)
V
IN
= V
SS
or V
CC
I
LI
Input Leakage Current
2
A
I
LO
Output Leakage Current
3
A
OUT
= 0V to V
CC
,
CS = 0V
V
IL
(3)
Input Low Voltage
-1
V
CC
x 0.3
V
V
IH
(3)
Input High Voltage
V
CC
x 0.7
V
CC
+ 0.5
V
V
OL1
Output Low Voltage
0.4
V
V
CC
<5.5V
I
OL
= 3.0mA
I
OH
= -1.6mA
V
OH1
Output High Voltage
V
CC
- 0.8
V
V
OL2
Output Low Voltage
0.2
V
1.8V
V
CC
<2.7V
V
OH2
Output High Voltage
V
CC
-0.2
V
I
OL
= 150
A
I
OH
= -100
A
Note:
(1) The minimum DC input voltage is –0.5V. During transitions, inputs may undershoot to –2.0V for periods of less than 20 ns. Maximum DC
voltage on output pins is V
CC
+0.5V, which may overshoot to V
CC
+2.0V for periods of less than 20 ns.
(2) Output shorted for no more than one second. No more than one output shorted at a time.
(3) This parameter is tested initially and after a design or process change that affects the parameter.
(4) Latch-up protection is provided for stresses up to 100 mA on address and data pins from –1V to V
CC
+1V.
Doc. No. 25067-00 5/00
2
C) ................................... 1.0W
Lead Soldering Temperature (10 secs) ............ 300
4.5V
Advanced Information
CAT25C01/02/04/08/16
Figure 1. Sychronous Data Timing
V
IH
t
CS
CS
V
IL
t
CSH
t
CSS
SCK
V
IH
t
WH
t
WL
V
IL
t
SU
t
H
V
IH
VALID IN
SI
V
IL
t
RI
t
FI
t
V
t
HO
t
DIS
SO
V
OH
HI-Z
HI-Z
V
OL
Note: Dashed Line= mode (1, 1) – ––––
A.C. CHARACTERISTICS
Limits
1.8V-6.0V
2.5V-6.0V
4.5V-5.5V
Test
SYMBOL PARAMETER
Min.
Max. Min.
Max. Min. Max. UNITS Conditions
t
SU
Data Setup Time
50
20
20
ns
V
IH
= 2.4V
t
H
Data Hold Time
50
20
20
ns
C
L
= 100pF
t
WH
SCK High Time
250
75
40
ns
V
OL
= 0.8V
t
WL
SCK Low Time
250
75
40
ns
V
OH
= 2.0v
f
SCK
Clock Frequency
DC
1
DC
5
DC
10
MHz
t
LZ
HOLD to Output Low Z
50
50
50
ns
t
RI
(1)
Input Rise Time
2
2
2
s
t
FI
(1)
Input Fall Time
2
2
2
s
t
HD
HOLD Setup Time
100
40
40
ns
t
CD
HOLD Hold Time
100
40
40
ns
C
L
= 100pF
C
L
= 50pF
t
WC
Write Cycle Time
10
5
5
ms
t
V
Output Valid from Clock Low
250
80
80
ns
t
HO
Output Hold Time
0
0
0
ns
t
DIS
Output Disable Time
250
75
75
ns
t
HZ
HOLD to Output High Z
150
50
50
ns
t
CS
CS High Time
500
100
100
ns
t
CSS
CS Setup Time
500
100
100
ns
t
CSH
CS Hold Time
500
100
100
ns
t
WPS
WP Setup Time
150
50
50
ns
t
WPH
WP Hold Time
150
50
50
ns
NOTE:
(1) This parameter is tested initially and after a design or process change that affects the parameter.
3
Doc. No. 25067-00 5/00
CAT25C01/02/04/08/16
Advanced Information
FUNCTIONAL DESCRIPTION
or data present on the SI pin are latched on the rising
edge of the SCK. Data on the SO pin is updated on the
falling edge of the SCK for SPI modes (0,0 & 1,1) .
The CAT25C01/02/04/08/16 supports the SPI bus data
transmission protocol. The synchronous Serial Periph-
eral Interface (SPI) helps the CAT25C01/02/04/08/16 to
interface directly with many of today’s popular
microcontrollers. The CAT25C01/02/04/08/16 contains
an 8-bit instruction register. (The instruction set and the
operation codes are detailed in the instruction set table)
CCS
:
Chip Select
CS is the Chip select pin. CS low enables the CAT25C01/
02/04/08/16 and CS high disables the CAT25C01/02/
04/08/16. CS high takes the SO output pin to high
impedance and forces the devices into a Standby Mode
(unless an internal write operation is underway) The
CAT25C01/02/04/08/16 draws ZERO current in the
Standby mode. A high to low transition on CS is required
prior to any sequence being initiated. A low to high
transition on CS after a valid write sequence is what
initiates an internal write cycle.
After the device is selected with CS going low, the first
byte will be received. The part is accessed via the SI pin,
with data being clocked in on the rising edge of SCK.
The first byte contains one of the six op-codes that define
the operation to be performed.
PIN DESCRIPTION
WWP
:
Write Protect
WP is the Write Protect pin. The Write Protect pin will
allow normal read/write operations when held high.
When WP is tied low and the WPEN bit in the status
register is set to “1”, all write operations to the status
register are inhibited. WP going low while CS is still low
will interrupt a write to the status register. If the internal
write cycle has already been initiated, WP going low will
have no effect on any write operation to the status
register. The WP pin function is blocked when the WPEN
bit is set to 0. Figure 10 illustrates the WP timing
sequence during a write operation.
SI:
Serial Input
SI is the serial data input pin. This pin is used to input all
opcodes, byte addresses, and data to be written to the
25C01/02/04/08/16. Input data is latched on the rising
edge of the serial clock for SPI modes (0, 0 & 1, 1).
SO:
Serial Output
SO is the serial data output pin. This pin is used to
transfer data out of the 25C01/02/04/08/16. During a
read cycle, data is shifted out on the falling edge of the
serial clock for SPI modes (0,0 & 1,1).
SCK:
Serial Clock
SCK is the serial clock pin. This pin is used to synchro-
nize the communication between the microcontroller
and the 25C01/02/04/08/16. Opcodes, byte addresses,
INSTRUCTION SET
Instruction
Opcode
Operation
WREN
0000 0110
Enable Write Operations
WRDI
0000 0100
Disable Write Operations
RDSR
0000 0101
Read Status Register
WRSR
0000 0001
Write Status Register
READ
0000 X011
(1)
Read Data from Memory
WRITE
0000 X010
(1)
Write Data to Memory
Power-Up Timing
(2)(3)
Symbol
Parameter
Max.
Units
t
PUR
Power-up to Read Operation
1
ms
t
PUW
Power-up to Write Operation
1
ms
Note:
(1) X=0 for 25C01, 25C02, 25C08, 25C16. X=A8 for 25C04
(2) This parameter is tested initially and after a design or process change that affects the parameter.
(3) t
PUR
and t
PUW
are the delays required from the time V
CC
is stable until the specified operation can be initiated.
Doc. No. 25067-00 5/00
4
CCS
CS
W
WP
WP
Advanced Information
CAT25C01/02/04/08/16
HOLD
:
Hold
STATUS REGISTER
HOLD is the HOLD pin. The HOLD pin is used to pause
transmission to the CAT25C01/02/04/08/16 while in the
middle of a serial sequence without having to re-transmit
entire sequence at a later time. To pause, HOLD must be
brought low while SCK is low. The SO pin is in a high
impedance state during the time the part is paused, and
transitions on the SI pins will be ignored. To resume
communication, HOLD is brought high, while SCK is low.
(HOLD should be held high any time this function is not
being used.) HOLD may be tied high directly to V
CC
or
tied to V
CC
through a resistor. Figure 9 illustrates hold
timing sequence.
The Status Register indicates the status of the device.
The RDY (Ready) bit indicates whether the CAT25C01/
02/04/08/16 is busy with a write operation. When set to
1 a write cycle is in progress and when set to 0 the device
indicates it is ready. This bit is read onlyThe WEL (Write
Enable) bit indicates the status of the write enable latch.
When set to 1, the device is in a Write Enable state and
when set to 0 the device is in a Write Disable state. The
WEL bit can only be set by the WREN instruction and can
be reset by the WRDI instruction.
STATUS REGISTER
7
6
5
4
3
2
1
0
WPEN
PR_MODE SPI_MODE
X
BP1
BP0
WEL
RDY
BLOCK PROTECTION BITS
Status Register Bits
Array Address
Protection
BP1
BP0
Protected
0
0
None
No Protection
0
1
25C01: 60-7F
Quarter Array Protection
25C02: C0-FF
25C04: 180-1FF
25C08: 0300-03FF
25C16: 0600-07FF
1
0
25C01: 40-7F
Half Array Protection
25C02: 80-FF
25C04: 100-1FF
25C08: 0200-03FF
25C16: 0400-07FF
1
1
25C01: 00-7F
Full Array Protection
25C02: 00-FF
25C04: 000-1FF
25C08: 0000-03FF
25C16: 0000-07FF
WRITE PROTECT ENABLE OPERATION
Protected
Unprotected
Status
WPEN
WP
WEL
Blocks
Blocks
Register
0
X
0
Protected
Protected
Protected
0
X
1
Protected
Writable
Writable
1
Low
0
Protected
Protected
Protected
1
Low
1
Protected
Writable
Protected
X
High
0
Protected
Protected
Protected
X
High
1
Protected
Writable
Writable
5
Doc. No. 25067-00 5/00
HOLD
WWP
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